1. Field of the Invention
This invention relates to a semiconductor device-testing apparatus, and more particularly to a semiconductor device-testing apparatus for testing a plurality of semiconductor devices simultaneously.
2. Description of the Related Art
Currently, an increasing number of semiconductor devices are designed and manufactured e.g. by ASIC (Application Specific Integrated Circuit) technology according to specifications demanded by users. In some cases, such semiconductor devices are subjected not only to tests by the designing and manufacturing sides, but also to tests, such as acceptance inspection, by the delivery side.
Semiconductor devices are generally mass-produced. Therefore, to improve the efficiency of testing semiconductor devices, there have been proposed semiconductor device-testing apparatuses which are each capable of testing a plurality of semiconductor devices simultaneously (see e.g. Japanese Laid-Open Patent Publication (Kokai) No. H11-64454 (page 4, and FIGS. 1 and 2)). Such semiconductor device-testing apparatuses are mainly used by the designing and manufacturing sides, for defect analysis, i.e. for analyzing which portion of a semiconductor device is defective.
On the delivery side, however, it is only required that the semiconductor device-testing apparatus is capable determining the quality of each semiconductor device, but it is not necessary that the apparatus has a high-functional testing capability. Therefore, there has been a demand for a semiconductor device-testing apparatus which is capable of testing semiconductor devices simultaneously by a simple construction.